1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device including a Subthreshold Current Reduction Circuit that reduces a leakage of a transistor.
Priority is claimed on Japanese Patent Application No. 2008-234863, filed Sep. 12, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been on the increase the requirement for small power voltage, high speed performance, and small power consumption of a semiconductor device such as a Dynamic Random Access Memory, hereinafter referred to as a DRAM. When the power voltage is lowered, it is necessary for ensuring the On-current of a transistor that the threshold voltage of the transistor be decreased in accordance with the scaling rule. The decrease of the threshold voltage of the transistor increases the Off-current and the current leakage.
Various circuits to reduce the current leakage have been proposed, for example, in Japanese Unexamined Patent Application, First Publications, Nos. 2000-195254, 2000-030443, and 2000-048568. One of the proposed circuits is a subthreshold current reduction circuit, hereinafter referred to as an SCRC. In the SCRC, two kinds of power lines such as a main power line and a sub power line are disposed. The main power line and the sub power line are connected to each other through metal oxide semiconductor transistors that each works as a switch. The metal oxide semiconductor transistor will hereinafter be referred to as a switching MOS transistor. When a memory bank is in an idle state that is a standby state, the switching MOS transistor turns into OFF to reduce the current leakage into the sub power line.